{"id":13747,"date":"2026-11-13T15:42:41","date_gmt":"2026-11-13T07:42:41","guid":{"rendered":"https:\/\/ascentoptics.com\/blog\/?p=13747"},"modified":"2026-11-13T15:42:41","modified_gmt":"2026-11-13T07:42:41","slug":"pam4-testing","status":"publish","type":"post","link":"https:\/\/ascentoptics.com\/blog\/pam4-testing\/","title":{"rendered":"PAM4 Testing and BER Measurement"},"content":{"rendered":"

A PAM4 module<\/u><\/a>\u00a0can pass every test on your bench and still ship a link with no margin left.<\/p>\n

That sentence sounds like a contradiction. It isn’t. Forward error correction used by 400G<\/a> and 800G<\/a> Ethernet links can correct transmission errors, but a passing BER result does not necessarily guarantee sufficient operating margin.\u00a0The number looks healthy. The margin is gone.<\/p>\n

If you test optical transceivers, you already know the standard measurements: optical power, extinction ratio, TDECQ, BER. What’s harder is knowing which of those numbers actually predicts whether a link survives a hot aisle, a long patch panel run, and eighteen months of laser aging.<\/p>\n

 <\/p>\n

 <\/p>\n

What Is PAM4 Testing?<\/strong><\/h2>\n

PAM4 testing is the process of verifying a four-level signal link against its standard. That covers transmitter quality measured as TDECQ, RLM, and OMA_outer, receiver performance measured as sensitivity and stressed sensitivity, and link quality measured as pre-FEC BER plus the FEC margin remaining after correction. Raw BER alone cannot prove a PAM4 link works.<\/p>\n

The definition matters because PAM4 splits what used to be one test into three. In NRZ, a single bit error rate told you most of what you needed. In PAM4, the transmitter, the receiver, and the link each have their own metrics, their own limits, and their own failure modes.<\/p>\n

Miss the split, and you get the classic result: a module with excellent TDECQ that fails in a switch, or a receiver that passes sensitivity but has almost no codeword headroom.<\/p>\n

 <\/p>\n

\"NRZ<\/p>\n

 <\/p>\n

 <\/p>\n

Why a Raw BER Number Is Not a Test Result<\/strong><\/h2>\n

Here’s where most PAM4 testing goes wrong. An engineer connects a module to a bit error rate tester, runs a pattern, reads a number, and compares it to a spec. The number passes. The module ships.<\/p>\n

The number was never the test.<\/p>\n

 <\/p>\n

Pre-FEC vs Post-FEC BER<\/strong><\/h3>\n

Pre-FEC BER<\/strong>\u00a0is the raw error rate on the physical link before correction. It reflects the link’s intrinsic quality: how clean the eye is, how much noise the receiver sees, how much the channel has smeared the signal.<\/p>\n

Post-FEC BER<\/strong>\u00a0is what remains after the decoder has done its work. This is what the host actually experiences.<\/p>\n

 <\/p>\n

Codeword Margin: The Number That Actually Decides<\/strong><\/h3>\n

KP4 FEC uses RS(544,514), which can correct up to 15 erroneous 10-bit RS symbols per codeword.<\/p>\n

At a pre-FEC BER of 1\u00d710\u207b\u2074, a 5,440-bit codeword contains an average of approximately 0.544 bit errors, assuming independent random errors. This does not imply that most codewords are approaching the FEC correction limit.<\/p>\n

However, average BER alone cannot fully describe link reliability. Correlated errors, error bursts, and the distribution of corrected symbols across codewords can significantly affect the probability of uncorrectable codewords.<\/p>\n

FEC-aware testing should therefore monitor pre-FEC BER, corrected-symbol distributions, and uncorrectable-codeword counts rather than relying on average BER alone.<\/p>\n

 <\/p>\n

Error Distribution and Burst Length<\/strong><\/h3>\n

Average BER hides one more thing, and it’s the one that breaks links: how the errors are grouped.<\/p>\n

Burst errors can be more challenging for FEC than independently distributed errors because they may concentrate multiple erroneous RS symbols within the same codeword. Their impact depends on the error mapping, codeword boundaries, and any interleaving used by the link.<\/p>\n

This is why the OIF electrical specifications define burst limits alongside BER limits. Depending on the reach class, they cap the maximum burst error length at roughly 15, 94, or 126 PAM4 symbols per 10\u00b2\u2070 symbols transmitted. Two links with identical BER can have wildly different real-world reliability, and the burst limit is what separates them.<\/p>\n

 <\/p>\n

\"KP4<\/p>\n

 <\/p>\n

 <\/p>\n

The Limits: What a Passing PAM4 Link Looks Like<\/strong><\/h2>\n

The limits live in four different places, which is why they’re so often misquoted. This table consolidates them. Verify each against the current clause before you put it in a specification.<\/p>\n

 <\/p>\n\n\n\n\n\n\n\n\n\n
Parameter<\/b><\/strong><\/td>\nOptical (100G\/lane)<\/b><\/strong><\/td>\nElectrical (OIF CEI)<\/b><\/strong><\/td>\nNotes<\/b><\/strong><\/td>\n<\/tr>\n
Pre-FEC BER<\/td>\n\u2264 2.4\u00d710\u207b\u2074 per lane<\/td>\n\u2264 1\u00d710\u207b\u2076 (VSR\/MR), \u2264 1\u00d710\u207b\u2074 (LR)<\/td>\nOptical limit aligns with KP4 correction capability<\/td>\n<\/tr>\n
Post-FEC BER<\/td>\n< 1\u00d710\u207b\u00b9\u00b3<\/td>\n< 1\u00d710\u207b\u00b9\u2075<\/td>\nInferred, not measured directly \u2014 see the duration section<\/td>\n<\/tr>\n
TDECQ<\/td>\n3.1 to 3.4 dB typical<\/td>\nNot applicable<\/td>\nLimit varies by PMD; check the clause table<\/td>\n<\/tr>\n
RLM<\/td>\nNot applicable<\/td>\n\u2265 0.95<\/td>\nElectrical transmitter linearity; optical uses TDECQ instead<\/td>\n<\/tr>\n
Burst error limit<\/td>\nGoverned by FEC<\/td>\n15 \/ 94 \/ 126 symbols per 10\u00b2\u2070<\/td>\nClass-dependent; FEC cannot fix long bursts<\/td>\n<\/tr>\n
Target SER for TDECQ<\/td>\n4.8\u00d710\u207b\u2074<\/td>\n\u2014<\/td>\nExactly 2\u00d7 the 2.4\u00d710\u207b\u2074 pre-FEC BER<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n

One caution on the right-hand column. The 200G-per-lane work in IEEE P802.3dj is still in draft, and its target numbers are moving. Module data presented to the task force shows a KP4 threshold below 2\u00d710\u207b\u2074 with operating pre-FEC targets in the 1\u00d710\u207b\u2074 to 1\u00d710\u207b\u2075 range. Treat every 200G\/lane figure as provisional and dated until the standard closes.<\/p>\n

 <\/p>\n

 <\/p>\n

Transmitter Testing: TDECQ, RLM, and OMA_outer<\/strong><\/h2>\n

Transmitter tests answer one question: is this module’s output clean enough that a standard receiver can recover it?<\/p>\n

 <\/p>\n

The Reference Receiver Decides Your TDECQ<\/strong><\/h3>\n

TDECQ stands for transmitter and dispersion eye closure, quaternary. It measures how much more optical power this transmitter needs than a perfect one to hit the target error ratio through a defined reference receiver.<\/p>\n

 <\/p>\n

The formula is:<\/p>\n

TDECQ = 10 \u00b7 log\u2081\u2080 (OMA_outer \/ (6 \u00b7 Q_t \u00b7 R))<\/strong><\/p>\n

Where Q_t is 3.414, corresponding to the 4.8\u00d710\u207b\u2074 target symbol error ratio, and R is the tolerable added noise reduced by the equalizer’s noise enhancement.<\/p>\n

 <\/p>\n

That reference receiver is the part engineers skim past, and it’s why two benches report different numbers for the same module. The standard specifies a fourth-order Bessel-Thomson filter at half the symbol rate: 26.5625 GHz at 53.125 GBd, and 53.125 GHz at 106.25 GBd. It also specifies a symbol-spaced feed-forward equalizer, five taps at 53.125 GBd and fifteen taps plus a one-tap decision feedback equalizer under the P802.3dj work at 106.25 GBd.<\/p>\n

Change the tap count, change the filter bandwidth, or let the equalizer search settle in a different place, and the reading moves. TDECQ is a specification, not a property of the module in isolation.<\/p>\n

The practical consequence: when a vendor quotes a TDECQ number, ask which reference receiver produced it. A 1.2 dB difference between two reports is usually methodology, not hardware.<\/p>\n

 <\/p>\n

RLM and the Four-Level Check<\/strong><\/h3>\n

RLM, the level mismatch ratio, asks whether the four output levels are evenly spaced. Uneven levels shrink one eye and grow another, and the smallest of the three is the one that fails first.<\/p>\n

It’s computed from the eye heights at the two inner levels relative to the outer ones, and normalized so a perfectly even transmitter scores 1.0. The electrical minimum in the 50G, 100G, and 200G per lane electrical specifications is 0.95. An older, looser 0.92 figure circulates from early drafts; don’t use it.<\/p>\n

RLM is commonly specified for PAM4 electrical transmitters, while TDECQ is a primary compliance metric for many PAM4 optical transmitters. The two metrics characterize different signal properties and are not interchangeable.<\/p>\n

 <\/p>\n

Overshoot, Undershoot, and Power Excursion<\/strong><\/h3>\n

Three smaller checks ride alongside TDECQ and are read from the same captures without the reference equalizer applied. Overshoot and undershoot quantify ringing at the outer levels and are typically capped near 22 percent of OMA_outer. Power excursion caps short-term average power swings.<\/p>\n

These rarely fail on their own. When one does, the transmitter is usually being overdriven or is bandwidth-starved, and TDECQ will already be showing the strain.<\/p>\n

 <\/p>\n

\"TDECQ<\/p>\n

 <\/p>\n

 <\/p>\n

Receiver Testing: Sensitivity, Stressed Sensitivity, and SECQ<\/strong><\/h2>\n

Receiver tests answer the other half: given a clean or deliberately impaired signal, how weak can the input get before the link breaks?<\/p>\n

 <\/p>\n

OMA_outer-Based Sensitivity<\/strong><\/h3>\n

Receiver sensitivity and stressed receiver sensitivity are distinct parameters.<\/p>\n

Receiver sensitivity characterizes receiver performance under defined reference signal conditions. Stressed receiver sensitivity evaluates the receiver using a calibrated impaired optical signal, including specified eye closure and other stress conditions.<\/p>\n

For example, stressed receiver sensitivity limits include \u22121.9 dBm for 100GBASE-DR, \u22122.5 dBm for 100GBASE-FR1, and \u22124.1 dBm for 100GBASE-LR1, expressed in OMAouter. These values must not be confused with the corresponding unstressed receiver sensitivity specifications.<\/p>\n

Both measurements must be evaluated against the applicable IEEE PMD requirements.<\/p>\n

 <\/p>\n

Stressed Receiver Sensitivity and the SECQ Penalty<\/strong><\/h3>\n

Sensitivity measured with a clean signal is a best case. Real links have penalties from dispersion, reflection, and transmitter imperfection. So the standards define stressed receiver sensitivity<\/strong>: the lowest OMA_outer at which the receiver meets its error criterion when fed a calibrated stressed signal.<\/p>\n

The stress is built from a defined set of impairments, and the calibration is the fiddly part. SECQ (Stressed Eye Closure for PAM4) characterizes the eye closure of the calibrated stressed optical signal used for receiver testing. Its measurement procedure and reference receiver settings are defined by the applicable IEEE specification.<\/p>\n

A receiver that passes clean sensitivity but fails stressed sensitivity has an equalization or front-end problem. It will work on a short patch cord and fail in the field, which is exactly the failure mode this test exists to catch.<\/p>\n

 <\/p>\n

The BER-versus-Attenuation Sweep<\/strong><\/h3>\n

For link-level work, sweep attenuation and record BER at each step. The curve tells you two things: where the link crosses the FEC threshold, and how steeply it does.<\/p>\n

A steep curve means the link is noise-limited and fails suddenly. A shallow curve means something else is limiting it, often a reflection or a marginal equalizer setting, and it will drift. Both fail. They need different fixes.<\/p>\n

 <\/p>\n

\"Receiver<\/p>\n

 <\/p>\n

 <\/p>\n

Test Patterns: PRBS13Q, PRBS31Q, and SSPRQ<\/strong><\/h2>\n

The pattern you transmit determines what the test can reveal. PAM4 uses three, and choosing the wrong one is a quiet way to pass a bad module.<\/p>\n

 <\/p>\n\n\n\n\n\n\n
Pattern<\/b><\/strong><\/td>\nLength<\/b><\/strong><\/td>\nWhat it stresses<\/b><\/strong><\/td>\nWhere it’s specified<\/b><\/strong><\/td>\nUsed for<\/b><\/strong><\/td>\n<\/tr>\n
PRBS13Q<\/td>\n8,191 PAM4 symbols<\/td>\nFast equalizer adaptation, deterministic jitter<\/td>\nIEEE 802.3, pattern 4<\/td>\nTransmitter linearity, some sensitivity tests<\/td>\n<\/tr>\n
PRBS31Q<\/td>\n2\u00b3\u00b9\u22121 symbols<\/td>\nLow-frequency effects, baseline wander<\/td>\nIEEE 802.3, pattern 3<\/td>\nReceiver sensitivity, aggressor lanes<\/td>\n<\/tr>\n
SSPRQ<\/td>\n65,535 symbols<\/td>\nWorst-case transition density<\/td>\nIEEE 802.3, pattern 6<\/td>\nTDECQ acquisition, stressed receiver calibration<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n

SSPRQ is a standardized 65,535-symbol stress pattern designed to capture challenging PAM4 sequences within a manageable acquisition length. It is widely used in TDECQ and stressed receiver measurements. Its purpose is to provide repeatable signal stress rather than to represent typical random payload data.<\/p>\n

A module that looks pristine under PRBS13Q can fail under SSPRQ. That isn’t a flaw in either test. It’s the reason production validation rarely relies on a single pattern.<\/p>\n

 <\/p>\n

 <\/p>\n

How Long Does a PAM4 Test Need to Run?<\/strong><\/h2>\n

This is the question that produces the most bad test reports, because the honest answer is uncomfortable.<\/p>\n

 <\/p>\n

The Three-Error Rule<\/b><\/strong><\/h3>\n

BER test duration depends on the target error rate, the actual bit rate, and the required statistical confidence.<\/p>\n

For a zero-error test, the one-sided 95% confidence upper bound on BER is approximately 3\/N, where N is the number of bits tested, assuming independent errors and a stationary link.<\/p>\n

To establish an upper bound of 1\u00d710\u207b\u00b9\u2075, approximately 3\u00d710\u00b9\u2075 bits must be transmitted without observed errors. This requires about 7.8 hours at 106.25 Gb\/s, or about 3.9 hours at 212.5 Gb\/s.<\/p>\n

The test must also distinguish between pre-FEC and post-FEC errors. Corrected errors do not count as post-FEC bit errors, although their frequency and distribution remain valuable indicators of link quality.<\/p>\n

For very low target BER values, practical validation often combines statistical testing, FEC error counters, receiver margin analysis, and stressed operating conditions.<\/p>\n

 <\/p>\n

\"BER<\/p>\n

 <\/p>\n

 <\/p>\n

Debugging a Marginal Link: The Diagnostic Order<\/strong><\/h2>\n

When a link comes up but won’t hold, guessing wastes days. Work the list in order. Each step rules out a class of causes.<\/p>\n

 <\/p>\n\n\n\n\n\n\n\n\n\n
Symptom<\/b><\/strong><\/td>\nLikely cause<\/b><\/strong><\/td>\nNext measurement<\/b><\/strong><\/td>\n<\/tr>\n
No pattern lock<\/td>\nReference clock, CDR bandwidth, or host equalizer setting<\/td>\nVerify the pattern and clock recovery configuration before touching the optics<\/td>\n<\/tr>\n
TDECQ over limit on one lane<\/td>\nDriver or laser issue on that lane<\/td>\nCompare tap weights across lanes; a busy tap set points to bandwidth, idle taps with wide histograms point to noise<\/td>\n<\/tr>\n
TDECQ passing, RLM failing<\/td>\nLevel mapping or driver linearity<\/td>\nRecheck the four-level spacing at the electrical test point<\/td>\n<\/tr>\n
Pre-FEC BER marginal, TDECQ clean<\/td>\nReceiver side, or channel loss<\/td>\nSweep attenuation; a shallow BER curve points to reflection or equalizer setting<\/td>\n<\/tr>\n
Errors clustered in bursts<\/td>\nChannel impairment rather than noise<\/td>\nCharacterize burst length against the class limit<\/td>\n<\/tr>\n
Passes at 25 \u00b0C, fails at 70 \u00b0C<\/td>\nThermal margin, not electrical margin<\/td>\nRepeat the full test at the top temperature corner<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n

That last row is the one people skip. A module meeting its limits on a bench at room temperature has demonstrated room-temperature compliance.<\/p>\n

 <\/p>\n

 <\/p>\n

Lab, Production Line, and Field: Three Different Tests<\/strong><\/h2>\n

The measurements don’t change across these three settings. The coverage does.<\/p>\n

Qualification<\/strong>\u00a0runs everything: per-lane TDECQ, RLM, OMA_outer, overshoot, sensitivity, stressed sensitivity, pre-FEC BER, burst distribution, and the full temperature matrix. Days per design.<\/p>\n

Production<\/strong>\u00a0runs a fast subset that correlates with the full suite. Per-lane pre-FEC BER at a fixed pattern and power, plus a TDECQ spot check, catches most escapes in minutes.<\/p>\n

Field<\/strong>\u00a0runs whatever the switch can tell you. FEC counters, per-lane error rates, and DOM readings are the signals available, which is why per-lane reporting matters so much at 800G. An aggregate counter on an eight-lane module hides one bad lane behind seven good ones.<\/p>\n

If a link fails in the field and the switch counters point at a specific lane, the next step is a bench test, not a replacement order. Our guide to\u00a0QSFP-DD troubleshooting<\/u><\/a>\u00a0walks through the field-side diagnosis that gets you to that decision.<\/p>\n

 <\/p>\n

 <\/p>\n

Frequently Asked Questions<\/strong><\/h2>\n

What is a good pre-FEC BER for PAM4?<\/b><\/strong><\/h3>\n

For 100G-per-lane optical links, the standard pre-FEC target is \u22642.4\u00d710\u207b\u2074, which KP4 FEC corrects to below 1\u00d710\u207b\u00b9\u00b3. A good number is well inside that limit with margin left in the codeword. Electrical interfaces use tighter targets: 1\u00d710\u207b\u2076 for very-short and medium reach, 1\u00d710\u207b\u2074 for long reach.<\/p>\n

How is PAM4 BER measured?<\/b><\/strong><\/h3>\n

With a bit error rate tester or a FEC-aware test instrument that generates a known pattern, compares the received symbols against the expected sequence, and counts mismatches. The pattern choice and the FEC mode matter as much as the instrument. Comparing raw errors without knowing the FEC state measures the wrong thing.<\/p>\n

Why is BER testing not enough for PAM4?<\/b><\/strong><\/h3>\n

Because FEC corrects errors, a passing average BER can coexist with near-zero correction headroom. Two links with identical BER can differ sharply in burst structure and in margin remaining. Codeword margin and burst length predict field behavior; average BER does not.<\/p>\n

What is TDECQ and how is it measured?<\/b><\/strong><\/h3>\n

TDECQ measures how much more optical power a transmitter needs than an ideal one to reach a 4.8\u00d710\u207b\u2074 symbol error ratio through a defined reference receiver. The receiver is a fourth-order Bessel-Thomson filter at half the symbol rate plus a symbol-spaced feed-forward equalizer. The result is reported in dB.<\/p>\n

What is the difference between TDECQ and TECQ?<\/b><\/strong><\/h3>\n

TECQ measures the same eye closure without the worst-case test fiber in the path, isolating the transmitter alone. TDECQ includes dispersion penalty. Plugfest specifications also cap the difference between the two, which catches transmitters that depend on the fiber to look good.<\/p>\n

What is the SSPRQ pattern used for?<\/b><\/strong><\/h3>\n

SSPRQ is a 65,535-symbol pattern built to produce the worst-case transition density for PAM4. It is the required pattern for TDECQ acquisition and for calibrating stressed receiver test signals. It is deliberately more stressful than random data, which is why modules that pass under PRBS13Q can fail under SSPRQ.<\/p>\n

How long should a PAM4 BER test run?<\/b><\/strong><\/h3>\n

Long enough to observe about three errors at the rate you’re proving, which gives roughly 95 percent confidence. That is about 28 seconds for 1\u00d710\u207b\u00b9\u00b2 and about 7.8 hours for 1\u00d710\u207b\u00b9\u2075 on a single 106.25 Gbps lane. Because 1\u00d710\u207b\u00b9\u2075 is impractical to measure, post-FEC performance is normally inferred from pre-FEC BER plus error distribution and FEC emulation.<\/p>\n

What is FEC-aware testing?<\/b><\/strong><\/h3>\n

Testing that accounts for the FEC in the link rather than counting raw errors alone. It includes measuring pre-FEC BER at the correct threshold, characterizing error bursts against the class limit, and using FEC emulation or a real decoder to project post-FEC performance and remaining margin.<\/p>\n

 <\/p>\n