\n| 1.6T 8-lane optics<\/td>\n | 8 \u00d7 200G<\/td>\n | 8 \u00d7 200G<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n <\/p>\n The actual configuration depends on the module architecture and host interface specification. Understanding this distinction is essential when evaluating gearbox requirements, breakout compatibility, and linear optical architectures.<\/p>\n <\/p>\n ![\"800G](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/11\/Electrical-and-Optical-Lane-Architecture.png\") <\/p>\n
<\/p>\n <\/p>\n What CEI-112G and CEI-224G Actually Define<\/strong><\/h2>\nThree standards bodies share this territory, and their documents answer different questions. The Optical Internetworking Forum (OIF) publishes the Common Electrical I\/O, or CEI, family. CEI defines electrical channels for die-to-die, chip-to-chip, and chip-to-module links.<\/p>\n IEEE defines the Ethernet attachment unit interface, or AUI, that a switch port presents. Multi-source agreements such as OSFP and QSFP-DD define the connector, cage, and module envelope.<\/p>\n <\/p>\n Reach Classes: XSR, VSR, MR, and LR<\/strong><\/h3>\nCEI groups channels by reach. XSR covers very short die-to-die links. VSR covers roughly 200 mm with one connector, which is typical for a chip-to-module path. MR extends to about 500 mm, and LR to about 1,000 mm with two connectors for backplane or passive copper.<\/p>\n For a pluggable module, VSR is the class that usually matters. When a vendor says a module meets CEI-112G-VSR, it means the module can close a short host channel under the defined test conditions. It doesn’t mean the module will close your channel.<\/p>\n <\/p>\n CEI-112G-Linear and the LPO Interface<\/strong><\/h3>\nThe linear specification is the one that changed module design. CEI-112G-Linear-PAM4 appears in\u00a0Clause 29 of the OIF CEI specification\u00a0and covers roughly 36 to 56 GBd. It sets a raw bit error rate of 2E-4 or better before FEC and a maximum host-to-module channel loss of 13 dB at 26.56 GHz.<\/p>\n The\u00a0LPO MSA specification\u00a0later extended that loss allowance to 16 dB for 100G-DR-LPO links. It also defined a module output electrical eye closure quaternary, or EECQ, limit of 7 dB. Those numbers are the contract between a linear module and a host. Miss them, and the link has no DSP to rescue it.<\/p>\n <\/p>\n CEI-224G: Draft Status, Shipping Silicon<\/strong><\/h3>\nCEI-224G electrical interfaces are being developed across multiple reach classes, including XSR, VSR, MR, LR, and Linear. While 224G-class SerDes and optical front-end components are emerging commercially, interoperability requirements continue to evolve. Buyers should verify the specific specification revision, implementation details, and platform-level compatibility.<\/p>\n That gap between draft and shipping product is normal, but buyers should treat it as a risk. Ask vendors which draft revision they designed against, and test against your own channel rather than relying on a compliance claim.<\/p>\n <\/p>\n <\/p>\n PAM4 SerDes Architectures: Retimer, Gearbox, CDR, and LPO<\/strong><\/h2>\nFour terms get mixed together constantly. They describe different jobs, and the differences explain most of the power and compatibility trade-offs in modern modules.<\/p>\n A clock and data recovery circuit, or CDR, extracts timing from the incoming signal and retimes it. It does not change lane rate or modulation. A retimer adds equalization and a clean transmit eye on top of that. A gearbox goes further and changes lane count or modulation, for example, converting eight 50G PAM4 host lanes into four 100G PAM4 optical lanes.<\/p>\n LPO, or linear pluggable optics, removes the module’s DSP and CDR entirely. The module keeps a driver and a linear receiver, and the host SerDes performs all equalization across the whole path.<\/p>\n <\/p>\n \n\n\nArchitecture<\/b><\/strong><\/td>\nWhat the module contains<\/b><\/strong><\/td>\nWhat the host must do<\/b><\/strong><\/td>\nRelative module power<\/b><\/strong><\/td>\nDiagnostics available<\/b><\/strong><\/td>\n<\/tr>\n\n| Fully retimed<\/td>\n | DSP in both directions<\/td>\n | Standard host equalization<\/td>\n | 100%<\/td>\n | Per-lane BER and SNR through module diagnostics<\/td>\n<\/tr>\n | \n| Half-retimed (RTLR or LRO)<\/td>\n | Retimed transmit, linear receive<\/td>\n | Host equalizes the receive path<\/td>\n | About 70%<\/td>\n | Partial<\/td>\n<\/tr>\n | \n| Linear (LPO)<\/td>\n | Driver and linear receiver only<\/td>\n | Host equalizes the entire link<\/td>\n | 50% to 70%<\/td>\n | Host FEC counters only<\/td>\n<\/tr>\n | \n| Co-packaged optics<\/td>\n | Optical engine beside the ASIC<\/td>\n | Depends on the design<\/td>\n | Lowest per bit<\/td>\n | Varies by platform<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n <\/p>\n Linear and half-retimed optical architectures can reduce module power consumption and processing latency by removing or simplifying DSP and retiming functions. The actual savings depend on data rate, optical reach, semiconductor process, host SerDes requirements, and module implementation. Power and latency should be compared using product-specific measurements and consistent system boundaries.<\/p>\n LPO modules generally provide fewer DSP-based signal diagnostics than fully retimed modules. Link-level BER and FEC statistics are typically monitored by the host, while module management interfaces may still provide temperature, voltage, optical power, bias current, and alarm information. Available diagnostic functions depend on the module implementation and management specification.<\/p>\n <\/p>\n ![\"Fully](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/11\/Fully-Retimed-vs.-LRO-vs.-LPO.png\") <\/p>\n
<\/p>\n <\/p>\n The Equalization Split: What Linear Optics Asks of the Host<\/strong><\/h2>\nIn a retimed module, equalization is a negotiation between two chips. In a linear module, it becomes a host responsibility, and the standard has to define exactly how much of the burden the host accepts.<\/p>\n On transmit, the host FIR is co-optimized with the module’s input continuous-time equalizer so the signal meets the TP1a specification. On receive, the host applies continuous-time linear equalization, feed-forward equalization, and decision feedback equalization at TP4. The module contributes only analog peaking in its driver and receiver.<\/p>\n Two electrical metrics quantify the result. EECQ measures eye closure through a reference equalizer, similar in spirit to TDECQ on the optical side. Ceeq measures noise enhancement from the equalizer, which matters because aggressive peaking can amplify noise as fast as it restores amplitude.<\/p>\n The practical consequence is a tighter channel budget. A retimed module can tolerate 16 dB or more of chip-to-module loss because its DSP can clean up the result. A linear module built to the base CEI specification is validated at 13 dB, and the LPO MSA’s 16 dB extension assumes a well-controlled channel. If your chassis has long traces, extra vias, or a lossy connector, linear optics may train on the bench and fail in the rack.<\/p>\n <\/p>\n <\/p>\n Why 224G Is Not Just 112G Doubled<\/strong><\/h2>\nDoubling the baud rate changes which impairments dominate and which design techniques still work.<\/p>\n At 106.25 GBd, the unit interval is 9.4 ps. The Nyquist frequency is 53.125 GHz. Jitter that was tolerable at 18.8 ps now consumes a much larger share of the eye. Package traces, connector pins, and even the module’s own PCB become significant low-pass filters.<\/p>\n <\/p>\n The 40 dB Die-to-Die Budget<\/strong><\/h3>\nIEEE P802.3dj addresses electrical interfaces operating at 200 Gb\/s per lane, including backplane, copper cable, and chip-to-module applications. The backplane objective supports a die-to-die insertion loss of up to 40 dB at 53.125 GHz. However, chip-to-module interfaces use separate channel models and compliance requirements. Engineers must evaluate insertion loss, reflections, crosstalk, and channel operating margin against the applicable interface specification.<\/p>\n At 224G-class signaling rates, higher channel loss and tighter timing margins make signal integrity more challenging. Retimers and active electrical cables can extend the usable reach of difficult channels. However, well-designed short-reach passive channels remain viable when the host SerDes, interconnect, and channel characteristics meet the applicable requirements.<\/p>\n <\/p>\n Error Performance and FEC<\/strong><\/h3>\nHigh-speed PAM4 Ethernet interfaces rely on forward error correction to achieve the required error performance. RS(544,514), commonly known as KP4 FEC, contains 514 information symbols and 30 parity symbols and can correct up to 15 symbol errors per codeword.<\/p>\n At 200 Gb\/s per lane, additional FEC architectures, including inner FEC for certain optical interfaces, may be used to address more demanding transmission conditions.<\/p>\n Electrical interface requirements also include application-specific detector error ratios, signal integrity limits, and channel operating margin. These parameters must be evaluated against the relevant IEEE or OIF specification rather than treated as universal requirements for all 112G- or 224G-class SerDes.<\/p>\n <\/p>\n <\/p>\n Frequently Asked Questions<\/strong><\/h2>\nWhat is a PAM4 SerDes?<\/b><\/strong><\/h3>\nA PAM4 SerDes is a serializer\/deserializer that transmits data using four-level PAM4 signaling. It converts parallel data to serial lanes, applies equalization, and recovers timing at the receiver. Each lane carries 2 bits per symbol, so a 53.125 GBd lane moves 106.25 Gbps.<\/p>\n What is the difference between 112G and 224G SerDes?<\/b><\/strong><\/h3>\nIn Ethernet applications, 112G-class PAM4 SerDes commonly operate at 53.125 GBd, delivering a raw lane rate of 106.25 Gb\/s. Emerging 224G-class Ethernet SerDes commonly operate at 106.25 GBd, delivering 212.5 Gb\/s per lane. The exact operating rate depends on the applicable electrical interface specification and protocol.<\/p>\n How many PAM4 SerDes lanes does 800G need?<\/b><\/strong><\/h3>\nEight lanes at 112G, or four lanes at 224G. The eight-lane design is the established 800GAUI-8 interface. The four-lane design uses 200G lanes and is increasingly common as 224G host SerDes ships.<\/p>\n What is CEI-112G?<\/b><\/strong><\/h3>\nCEI-112G is the OIF Common Electrical I\/O specification for roughly 112 Gbps PAM4 electrical links. It defines channel classes such as VSR, MR, and LR, along with test points, loss budgets, and error-ratio targets. IEEE 802.3ck defines the related 100G-per-lane Ethernet interface.<\/p>\n What is the difference between a retimer and a gearbox?<\/b><\/strong><\/h3>\nA retimer restores timing and amplitude while preserving lane rate and modulation. A gearbox changes lane count or modulation, such as converting eight 50G PAM4 lanes into four 100G PAM4 lanes. Many module DSPs can operate in either mode.<\/p>\n What is CEI-112G-Linear?<\/b><\/strong><\/h3>\nCEI-112G-Linear-PAM4 is the OIF specification for linear, DSP-less module interfaces used by LPO. It pushes most equalization into the host SerDes and sets a 13 dB host-to-module loss budget at 26.56 GHz, later extended to 16 dB by the LPO MSA.<\/p>\n Does 224G PAM4 SerDes always require a retimer?<\/b><\/strong><\/p>\nNo. Retimers can improve signal integrity in high-loss channels, but short, well-designed passive channels may operate without additional retiming. The requirement depends on the electrical interface and channel budget.<\/p>\n Is CEI-224G finished?<\/b><\/strong><\/h3>\nNot fully. The CEI-224G framework and reach classes are defined, and the LR and MR drafts were at revision 12 in April 2026. CEI-224G-Linear is still a draft, although compliant silicon is already shipping. Verify the revision a vendor designed against.<\/p>\n <\/p>\n | | | | | | |
![\"Host,](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/11\/Host-Electrical-Channel-and-Optical-Module.png\")
<\/p>\n![\"112G](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/11\/112G-vs.-224G-PAM4-SerDes.png\")
<\/p>\n