{"id":13636,"date":"2026-11-03T15:32:08","date_gmt":"2026-11-03T07:32:08","guid":{"rendered":"https:\/\/ascentoptics.com\/blog\/?p=13636"},"modified":"2026-11-03T15:32:08","modified_gmt":"2026-11-03T07:32:08","slug":"pam4-modulation","status":"publish","type":"post","link":"https:\/\/ascentoptics.com\/blog\/pam4-modulation\/","title":{"rendered":"PAM4 Modulation: The Complete Guide to 4-Level Pulse Amplitude Modulation"},"content":{"rendered":"

PAM4 has become a key signaling technology in modern high-speed optical transceivers, particularly in 400G and 800G applications. By encoding two bits per symbol, PAM4 doubles the data rate compared with NRZ at the same baud rate, enabling higher bandwidth without proportionally increasing the number of transmission lanes.<\/p>\n

You already know PAM4 matters, even if you have never dissected it. You see it in every “400G DR4” and “800G SR8” spec you evaluate. What you may not have seen is a clear explanation of how the signal actually works, why it demands a DSP and forward error correction, and what that means when you choose a transceiver.<\/p>\n

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What Is PAM4?<\/strong><\/h2>\n

PAM4 is a signaling method that encodes data into four distinct amplitude levels, carrying two bits of information in every transmitted symbol instead of the single bit carried by traditional NRZ.<\/p>\n

PAM4 stands for 4-level Pulse Amplitude Modulation<\/strong>. In a conventional NRZ (non-return-to-zero) signal, the transmitter chooses between two voltage levels: a low level for a binary 0 and a high level for a binary 1. One symbol, one bit. PAM4 adds two intermediate levels, giving the transmitter four options per symbol. Because four levels can represent four two-bit combinations (00, 01, 11, and 10), each PAM4 symbol carries twice as much information as an NRZ symbol at the same baud rate.<\/p>\n

The cost of that doubling is signal margin. When you squeeze four levels into the same voltage range that NRZ uses for two, the levels sit one-third as far apart. Noise that NRZ would shrug off can push a PAM4 level across a decision threshold and corrupt a bit. That is why PAM4 is inseparable from the DSP equalization and forward error correction covered later in this guide.<\/p>\n

For a concrete sense of scale, consider the transition the industry already made. A 100GBASE-LR4 module uses four 25G NRZ lanes. A 400G DR4 module uses four 100G PAM4 lanes. Same lane count, four times the throughput. PAM4 is the difference.<\/p>\n

Related<\/strong>: To see how this maps to a specific speed generation, start with our What Is 800G?<\/u><\/a><\/p>\n

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\"NRZ<\/p>\n

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How PAM4 Works: Symbol Mapping and Gray Coding<\/strong><\/h2>\n

Four Levels, Two Bits: The PAM4 Symbol Alphabet<\/strong><\/h3>\n

PAM4 defines four amplitude levels, conventionally labeled from lowest to highest. Each level maps to a two-bit value. The mapping is not arbitrary, and getting it wrong in a diagram is a fast way to lose an engineering audience.<\/p>\n

The standard mapping assigns the levels in this order, from lowest voltage to highest:<\/p>\n

    \n
  1. Level 0: 00<\/li>\n
  2. Level 1: 01<\/li>\n
  3. Level 2: 11<\/li>\n
  4. Level 3: 10<\/li>\n<\/ol>\n

    Notice the pattern: the two-bit values follow Gray code<\/strong>\u00a0order, not binary counting order. Binary counting would go 00, 01, 10, 11. Gray code deliberately swaps the last two so that adjacent levels always differ by exactly one bit.<\/p>\n

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    Gray Coding and Why It Minimizes Bit Errors<\/strong><\/h3>\n

    Gray coding minimizes the number of bit errors caused by incorrect decisions between adjacent PAM4 levels. Since neighboring levels differ by only one bit, a typical adjacent-level symbol error results in a single-bit error rather than multiple bit errors. This helps reduce the overall bit error rate and improves the effectiveness of the transmission system when combined with FEC.<\/p>\n

    That single detail measurably improves the post-FEC bit error rate, because forward error correction fixes isolated single-bit errors far more efficiently than bursts. The 00, 01, 11, 10 pattern is not a stylistic choice. It is an error-resilience optimization built directly into the modulation format.<\/p>\n

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    Baud Rate vs Bit Rate<\/strong><\/h3>\n

    PAM4 decouples two numbers that engineers often blur together. The baud rate<\/strong>\u00a0is the number of symbols per second. The bit rate<\/strong>\u00a0is the number of bits per second. With PAM4, the bit rate is always double the baud rate.<\/p>\n

    A typical 100G PAM4 lane operates at 53.125 GBd. Since each symbol carries two bits, the gross signaling rate is 106.25 Gbps. After accounting for FEC and other protocol overhead, the lane supports a nominal 100 Gbps data rate. This distinction explains why the baud rate and the effective data rate are not identical.<\/p>\n

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    PAM4 vs NRZ: Key Differences<\/strong><\/h2>\n

    The cleanest way to understand PAM4 is to place it next to the NRZ signaling it replaced.<\/p>\n

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    The SNR Penalty Explained<\/strong><\/h3>\n

    PAM4 has a smaller voltage separation between adjacent signal levels than NRZ when both use the same overall signal swing. This reduces the noise margin and makes PAM4 more sensitive to noise and distortion. A commonly cited theoretical SNR penalty is approximately 9.5 dB under specific comparison conditions, although the actual system-level penalty depends on the receiver design, signal quality, and FEC implementation.<\/p>\n

    That penalty is partially offset by the fact that PAM4 needs only half the baud rate for the same bit rate, which reduces bandwidth-related noise. But the net result is unchanged: PAM4 is a noisier, more fragile signal that only works because the industry paired it with DSP equalization and strong forward error correction.<\/p>\n

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    \"PAM4<\/p>\n

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    Three Decision Thresholds Instead of One<\/b><\/strong><\/h3>\n

    NRZ has a single decision threshold. The receiver asks one question: is the sample above or below the midpoint? PAM4 asks three questions, one at each boundary between adjacent levels. Three thresholds means three times the opportunities for a noise spike to land on the wrong side. That is why a PAM4 eye diagram shows three stacked eyes rather than the single eye of NRZ.<\/p>\n

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    When Each Modulation Format Makes Sense<\/b><\/strong><\/h3>\n\n\n\n\n\n\n\n\n\n
    Attribute<\/b><\/strong><\/td>\nNRZ<\/b><\/strong><\/td>\nPAM4<\/b><\/strong><\/td>\n<\/tr>\n
    Bits per symbol<\/td>\n1<\/td>\n2<\/td>\n<\/tr>\n
    Amplitude levels<\/td>\n2<\/td>\n4<\/td>\n<\/tr>\n
    Baud rate for 100G per lane<\/td>\nN\/A (25G per lane typical)<\/td>\n53.125 GBd<\/td>\n<\/tr>\n
    SNR requirement<\/td>\nLower<\/td>\n~9.5 dB higher at same baud<\/td>\n<\/tr>\n
    DSP\/FEC required<\/td>\nUsually not<\/td>\nMandatory<\/td>\n<\/tr>\n
    Typical speeds<\/td>\n10G, 25G, 100G (LR4)<\/td>\n50G, 100G, 200G per lane<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

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    NRZ remains the right tool at 10G and 25G per lane, where its simplicity and signal margin outweigh its lower spectral efficiency. PAM4 takes over at 50G per lane and above, where doubling bits per symbol is the only practical way to push more bandwidth through existing lanes without doubling the number of lasers and fibers.<\/p>\n

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    Why PAM4 Needs DSP and FEC<\/strong><\/h2>\n

    PAM4 signals are more sensitive to noise, distortion, and inter-symbol interference than NRZ signals. In conventional DSP-based optical transceivers, digital signal processing plays an important role in compensating for channel impairments and improving signal quality. However, alternative architectures such as LPO reduce or eliminate the module-side DSP by relying more heavily on host-side signal processing.<\/p>\n

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    Noise, Dispersion, and Inter-Symbol Interference<\/b><\/strong><\/h3>\n

    A PAM4 signal degrades as it travels through a PCB trace, a connector, or a length of fiber. High-frequency loss rounds off the sharp transitions between levels. Chromatic dispersion smears symbols in time so that one symbol bleeds into the next, a phenomenon called inter-symbol interference (ISI). Because PAM4 levels are already close together, even modest ISI can close the eye completely.<\/p>\n

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    DSP Equalization: CTLE, FFE, and DFE<\/b><\/strong><\/h3>\n

    A digital signal processor inside the transceiver reverses much of that damage. The equalization chain typically includes three stages:<\/p>\n