The performance differences among AI interconnect technologies fundamentally stem from their underlying architectural design principles. Memory-semantic\u2013driven UAL and Ethernet-ecosystem\u2013compatible derivatives (including UALoE\/SUE and RoCE) differ significantly in their base design logic and architectural implementation. These differences directly determine their behavior in key metrics such as load balancing, latency control, and bandwidth utilization:<\/p>\n
UAL:<\/strong> A dedicated, AI-optimized memory-semantic interconnect designed to achieve ultra-low latency and maximum efficiency.<\/p>\n UALoE \/ SUE:<\/strong> Combines memory semantics with Ethernet headers, striking a balance between performance and ecosystem compatibility.<\/p>\n RoCE:<\/strong> An RDMA-based Ethernet technology that leverages a mature ecosystem and focuses on high-throughput, bulk data transfer scenarios.<\/p>\n <\/p>\n <\/p>\n UAL is a memory-semantic interconnect technology specifically designed for AI scale-out architectures, with the core objective of eliminating redundant overhead in data transmission. Its key design features include:<\/p>\n No Ethernet dependency:<\/strong> Data is transmitted directly based on memory semantics without Ethernet encapsulation, reducing protocol-layer overhead.<\/p>\n No packetization\/depacketization logic:<\/strong> Uses a fixed 640-byte flit design, eliminating the need to aggregate transactions into packets and significantly reducing hardware area, power consumption, and latency.<\/p>\n No RTT latency:<\/strong> Employs a compute-layer push model\u2014DMA engines are deployed within Compute Tiles (CTs) and directly initiate inter-XPU data transfers without waiting for Network Tiles (NTs) to pull data, thereby avoiding round-trip latency.<\/p>\n High load-balancing efficiency:<\/strong> Based on 256-byte transaction\u2013level fine-grained balancing, ensuring optimal lane utilization across all transfer sizes (256B\u20134096B). This is especially well suited for small-batch, high-frequency AI traffic.<\/p>\n High fault tolerance:<\/strong> Supports multi-lane port degradation, maintaining up to 50% bandwidth even in the event of a single-lane failure, ensuring uninterrupted workloads.<\/p>\n In addition, UAL requires only the potential addition of a lightweight shim (adaptation layer) to convert the memory-semantic interface into a UPLI interface, simplifying hardware integration.<\/p>\n <\/p>\n <\/p>\n UALoE\/SUE is a compromise solution designed for compatibility with the Ethernet ecosystem. Its core approach is to encapsulate an optimized Ethernet header in memory-semantic transmissions, preserving the high efficiency of UAL while enabling seamless integration into existing Ethernet infrastructure.<\/p>\n <\/p>\n Inheritance of UAL’s High-Efficiency Genes:<\/strong> It retains UAL’s 256B transaction-level load balancing and compute-layer Push model. For small transfers (256B\u2013512B), bandwidth efficiency is close to that of pure UAL, with zero RTT (round-trip time) latency.<\/p>\n Optimized Ethernet Header:<\/strong> Uses a streamlined 14B Ethernet header combined with an 8B request + 4B response (total overhead of 26B). This is significantly lower than traditional Ethernet’s redundant designs, minimizing the performance penalty from compatibility requirements.<\/p>\n On-Demand Packet Aggregation Mechanism:<\/strong> The sender and receiver must aggregate small transactions into larger packets for transmission (e.g., 512B and above). While this introduces some packing overhead, bandwidth can match UAL levels for \u2265512B transfers. If the Ethernet inter-frame gap (IPG) is further reduced from 20B, the performance gap can be completely eliminated.<\/p>\n Native Ecosystem Compatibility:<\/strong> Directly compatible with existing Ethernet switches and NICs, requiring no major reconstruction of cluster networks. This greatly reduces upgrade costs for enterprises, making it especially suitable for AI clusters already built on Ethernet infrastructure.<\/p>\n In summary, UALoE\/SUE (where UALoE likely stands for “UAL over Ethernet” and SUE refers to Broadcom’s Scale-Up Ethernet) represents a practical bridge between proprietary high-performance protocols (like UALink\/UAL) and the widely deployed Ethernet ecosystem. It targets scale-up AI networking, balancing near-native efficiency for memory operations with broad interoperability and lower deployment barriers. This makes it an attractive option for AI\/HPC environments transitioning toward standardized, cost-effective interconnects.<\/p>\n <\/p>\n <\/p>\n RoCE (RDMA over Converged Ethernet) is an Ethernet-based interconnection solution built on RDMA technology. It leverages a mature RDMA ecosystem and excels in bulk data transfer scenarios, but it has clear shortcomings in AI small-packet (small transfer) workloads.<\/p>\n <\/p>\n Block-Level Load Balancing:<\/strong> RoCE employs block-level data distribution, which is only suitable for bulk transfers of \u22652048B. For small-sized transfers (<1024B), it easily leads to channel imbalance, resulting in bandwidth utilization below 50%.<\/p>\n Network-Layer Pull Model:<\/strong> DMA threads are deployed in the Network Tile (NT), requiring data to be pulled from the Compute Tile (CT). This introduces a fixed startup overhead of 240ns + a base processing latency of 440ns. Additionally, reordering jitter (~400ns) increases with packet size.<\/p>\n Reliability Dependent on ACK\/NACK:<\/strong> It relies on Selective ACK\/NACK mechanisms to ensure transmission reliability. Without link-layer retry support, higher-layer mechanisms are needed to compensate, leading to high complexity in fault handling (e.g., requiring connection remapping).<\/p>\n In summary, while RoCE provides excellent performance for large-scale, high-throughput data movements in traditional HPC and storage applications (thanks to low CPU involvement and high bandwidth), its design\u2014rooted in block-oriented handling, pull-based initiation from the network side, and dependency on selective acknowledgments\u2014makes it less efficient for the frequent, small-message communications typical in modern AI training workloads (e.g., gradient synchronization in distributed models). This has driven interest in newer alternatives like UALink, Ultra Ethernet, or optimized Ethernet variants (e.g., UALoE\/SUE) that better address small-packet efficiency, push models, and reduced overhead for AI\/HPC scale-up scenarios.<\/p>\n <\/p>\n The report conducts a quantitative comparison of the three technologies across three major dimensions: workflow, functionality, and attributes. The core differences are summarized in the tables below.<\/p>\n Table 1: Workflow Differences Comparison<\/strong><\/p>\n <\/p>\n <\/p>\n Table 2: Functionality Differences Comparison<\/strong><\/p>\n <\/p>\n <\/p>\n Table 3: Attributes Differences Comparison<\/strong><\/p>\n <\/p>\n <\/p>\n The core bottleneck of bandwidth efficiency lies in header overhead and packet aggregation strategy. The three technologies exhibit significant performance differences under varying packet sizes:<\/p>\n <\/p>\n <\/p>\n UAL: Maintains optimal efficiency across all scenarios.<\/strong><\/p>\n With no additional headers whatsoever, UAL achieves near-theoretical-maximum bandwidth efficiency for both small 256-byte packets and large multi-KB packets. There is virtually no efficiency loss caused by excessive header overhead.<\/p>\n UALoE\/SUE: Efficiency varies dynamically with packet size.<\/strong><\/p>\n In small-packet scenarios (below 256 bytes), the 14-byte Ethernet header takes up a disproportionately large portion, resulting in bandwidth efficiency of only 60%\u201370% of pure UAL.<\/p>\n When packet size increases to 512\u2013768 bytes, aggregation of multiple memory transactions helps amortize the header overhead, raising efficiency to approximately 90% of UAL \u2014 but it can never fully match UAL\u2019s performance.<\/p>\n RoCE: Starts with the lowest efficiency and has a limited ceiling.<\/strong><\/p>\n In small-packet scenarios, the combination of multi-layer headers and ACK overhead drives efficiency below 50% of UAL.<\/p>\n Even when MTU (Maximum Transmission Unit) is set to the maximum value, the continuous overhead introduced by the ACK mechanism keeps peak efficiency noticeably lower than both UAL and UALoE\/SUE.<\/p>\n <\/p>\n Latency is a critical metric for large-scale AI training (e.g., parameter exchange\/synchronization) and real-time inference. The three technologies exhibit clearly distinct latency characteristics:<\/p>\n <\/p>\n <\/p>\n UAL: Lowest latency with zero jitter.<\/strong><\/p>\n It delivers a fixed latency of only 300 nanoseconds (200 ns in the switch + 100 ns at the accelerator side). Regardless of the number of connections or packet sizes, latency remains perfectly stable \u2014 fully meeting the stringent low-latency requirements of demanding AI workloads.<\/p>\n UALoE\/SUE: Higher latency with noticeable jitter.<\/strong><\/p>\n Baseline latency is 400 nanoseconds (including 100 ns of packing overhead). When the number of concurrent connections increases to 32 or more, deeper packet aggregation is required to improve bandwidth efficiency, causing latency to rise above 500 nanoseconds. Jitter can reach up to 100 nanoseconds.<\/p>\n RoCE: Highest latency with strong uncertainty.<\/strong><\/p>\n Baseline latency exceeds 600 nanoseconds, and as transaction size grows, additional variable delays are introduced from data pull operations, reordering, ACK waiting, and other stages. Jitter can reach microsecond levels, making it difficult to satisfy the strict latency stability demands of modern AI scenarios.<\/p>\n <\/p>\n UAL offers the best-in-class deterministic, ultra-low latency \u2014 ideal for latency-sensitive AI\/HPC workloads.<\/p>\n UALoE\/SUE represents a practical trade-off: slightly higher and less stable latency in exchange for Ethernet compatibility.<\/p>\n RoCE suffers the most in both average latency and jitter, especially under the small, frequent message patterns typical of AI training.<\/p>\n <\/p>\n Based on the performance comparison results, the applicable boundaries of the three technologies are clearly defined.<\/p>\n UAL:<\/strong> Best suited for latency-sensitive, bandwidth-intensive core workloads, such as gradient exchange in tens-of-thousands-GPU AI training and data transfer in real-time inference. It is particularly ideal for ultra-large-scale AI clusters that pursue maximum performance.<\/p>\n <\/p>\n UALoE \/ SUE:<\/strong> Appropriate for scenarios that require compatibility with existing Ethernet infrastructure and have lower latency sensitivity, such as non-real-time AI inference, data backup, and data migration. It serves as a transitional solution between UAL and the Ethernet ecosystem.<\/p>\n <\/p>\n RoCE:<\/strong> Recommended for general-purpose RDMA use cases in traditional data centers. In large-scale AI computing environments, it is best suited only for non\u2013performance-critical auxiliary data transfers.<\/p>\n <\/p>\n As AI compute capability continues to scale rapidly, interconnect technology has evolved from a supporting component into a core competitive differentiator. With its ultra-low latency and high bandwidth efficiency, UAL is poised to become a mainstream choice for future ultra-large-scale AI clusters, while ongoing optimization of UALoE\/SUE and RoCE will provide greater flexibility across diverse infrastructure environments. Looking ahead, continued protocol standardization and architectural innovation will further unlock AI computing potential and drive large-scale AI applications to the next level of maturity.<\/p>\n <\/p>\n <\/p>\n","protected":false},"excerpt":{"rendered":" As AI computing scales toward tens-of-thousands-GPU clusters, interconnect technology has become a core bottleneck limiting performance, directly determining the efficiency of AI training and inference. Based on recent presentations released by the Open Compute Project (OCP), this article provides a comprehensive analysis of three mainstream interconnect technologies\u2014Ultra Accelerator Link (UAL), Ethernet-based UALoE\/SUE (UAL over Ethernet), […]<\/p>\n","protected":false},"author":1,"featured_media":11647,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":"","_wpscp_schedule_draft_date":"","_wpscp_schedule_republish_date":"","_wpscppro_advance_schedule":false,"_wpscppro_advance_schedule_date":"","_wpscppro_custom_social_share_image":0,"_facebook_share_type":"default","_twitter_share_type":"default","_linkedin_share_type":"default","_pinterest_share_type":"default","_linkedin_share_type_page":"","_instagram_share_type":"default","_selected_social_profile":null},"categories":[1],"tags":[],"class_list":["post-11634","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technology"],"yoast_head":"\n![\"Scale](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/01\/\u56fe1.png\")
<\/p>\nUAL<\/strong><\/h2>\n
![\"XPU](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/01\/\u56fe2.png\")
<\/p>\nUALoE\/SUE<\/strong><\/h2>\n
Key Features:<\/strong><\/h3>\n
![\"XPU](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/01\/\u56fe3.png\")
<\/p>\nRoCE<\/strong><\/h2>\n
Key Limitations:<\/strong><\/h3>\n
![\"Table](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/01\/\u88681.png\")
<\/p>\n![\"Table](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/01\/\u88682.png\")
<\/p>\n![\"Table](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/01\/\u88683.png\")
<\/p>\nPerformance Benchmarking<\/strong><\/h2>\n
Bandwidth Efficiency: Packet Size Determines the Efficiency Ceiling<\/strong><\/h3>\n
![\"Performance](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/01\/\u6027\u80fd\u5b9e\u6d4b.png\")
<\/p>\nLatency Performance: A Stark Contrast in Determinism and Jitter<\/strong><\/h3>\n
![\"Latency](\"https:\/\/ascentoptics.com\/blog\/wp-content\/uploads\/2026\/01\/\u5ef6\u8fdf\u8868\u73b0.png\")
<\/p>\nIn short:<\/strong><\/h3>\n
Technology Selection<\/strong><\/h2>\n
Conclusion<\/strong><\/h2>\n